Articles with tag 'RISC-V'

Microcontroller Thumbnail

As part of Codethink's interest in RISC-V I have been following the RISC-V kernel list. Whilst looking through the postings the following bug came up, titled: [syzbot] BUG: unable to handle kernel access to user memory in schedule_tail

RISC-V Thumbnail

When something as exciting as a completely open CPU architecture comes along, it's hard to stop Codethink's engineers from getting involved. We've set up an internal research project with the goal of learning about RISC-V, and we have some interesting results already.

Meet the Codethings: Ben Dooks talks about Linux kernel and RISC-V Thumbnail

Ben Dooks is our Senior Engineer and Open Source Consultant with more than 15 years’ experience contributing to Linux Kernel. Dooks joined Codethink 8 years ago, and since then he's been involved in a range of projects involving the Linux kernel, such as the MEG project, amongst others.

RISC-V is a new Instruction Set Architecture developed in the open and available for use without paying a license fee. This means there are no barriers to achieving open hardware implementations, which opens the door to performant (mostly) open hardware processors...

Tag Index

Get in touch to find out how Codethink can help you

sales@codethink.co.uk +44 161 660 9930