Articles with tag 'RISC-V'

Automated Kernel Testing on RISC-V Hardware

Thu 21 September 2023 - Neill Whillans

Continuing our work on robust testing in support of long-term maintainability, we present a testing pipeline that makes use of both LAVA and OpenQA to perform automated kernel tests on RISC-V hardware.

RISC-V: Exploring a Bug in Stack Unwinding

Thu 08 June 2023 - Ben Dooks

On one of our RISC-V projects, we were recently debugging a complex driver probing sequence in the U-Boot bootloader. Along the way we improved the debugging facilities available for U-Boot on RISC-V, specifically allowing developers and system integrators to see the callstack in the case that there is a crash during the early boot sequence.

Adding RISC-V Vector Cryptography Extension support to QEMU

Fri 02 June 2023 - Lawrence Hunter, Nazar Kazakov, Kiran Ostrolenk, Dickon Hood

A dive into our work to add further support for vector cryptography in RISC-V with QEMU!

Codethink proudly sponsors GUADEC 2022

Tue 19 July 2022 - Javier Jardón

Codethink is happy to sponsor GUADEC one year more

Protecting your project from dependency access problems

Wed 26 January 2022 - Kyle Mckay, Ellis Barnwell

The problem with introducing these dependencies, is that part of your project now exists outside of your control.

Porting GNOME OS to Microchip's PolarFire Icicle Kit

Thu 25 November 2021 - Michael Drake, Robin J. Heywood

We've ported GNOME OS to the PolarFire Icicle-Kit Devboard from Microchip.

RISC-V: running GNOME OS on SiFive hardware for the first time

Tue 28 September 2021 - Valentin David, Sam Thursfield

Codethink continues to participate in the promising RISC-V ecosystem, and we have exciting news around Freedesktop SDK and GNOME.

RISC-V: A Small Hardware Project

Thu 15 July 2021 - Robin J. Heywood

As part of Codethink's interest in RISC-V, we created some simple hardware.

RISC-V User space access Oops

Wed 21 April 2021 - Ben Dooks

As part of Codethink's interest in RISC-V I have been following the RISC-V kernel list. Whilst looking through the postings the following bug came up, titled: [syzbot] BUG: unable to handle kernel access to user memory in schedule_tail

RISC-V: Codethink's first research about the open instruction set

Thu 11 February 2021 - Sam Thursfield

When something as exciting as a completely open CPU architecture comes along, it's hard to stop Codethink's engineers from getting involved. We've set up an internal research project with the goal of learning about RISC-V, and we have some interesting results already.

Meet the Codethings: Ben Dooks talks about Linux kernel and RISC-V

Tue 05 January 2021 - Yasmin Ferreras Greenwood, Ben Dooks

Ben Dooks is our Senior Engineer and Open Source Consultant with more than 15 years’ experience contributing to Linux Kernel. Dooks joined Codethink 8 years ago, and since then he's been involved in a range of projects involving the Linux kernel, such as the MEG project, amongst others.

Improving RISC-V Linux support in Rust

Tue 02 June 2020 - Tom Eccles

RISC-V is a new Instruction Set Architecture developed in the open and available for use without paying a license fee. This means there are no barriers to achieving open hardware implementations, which opens the door to performant (mostly) open hardware processors...