RISC-V Summit Europe 2025 is just around the corner (12-15 May), and we’re excited to present a technical presentation and a poster exhibition. Learn out more about where and when you can find us below.
Talk: ‘Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions’
Join Lawrence Hunter, Roan Richmond, and Ben Dooks as they dive into the intricacies of implementing dynamic endianness support in RISC-V.
Talk information:
Session T2.3.06 (Submission #105)
Date: Wednesday 14 May at 12:45
Location: Gaston Berger (S2)
Abstract:
The RISC-V Privileged Specification introduced dynamic endianness switching in version 1.12, though no commercial hardware yet supports it. This work extends QEMU to enable big-endian execution, allowing the booting of a big-endian Linux system with OpenSBI. Modifications were required across QEMU, OpenSBI, the Linux kernel, and supporting libraries to ensure correct memory operations, instruction encoding, and runtime patching. The project demonstrates the feasibility of big-endian support for RISC-V, providing a foundation for future hardware and software development.
Poster Exhibition:
Come and chat with our engineers during the poster session on Tuesday, 13 May, when we’ll showcase this work in further detail.
Location: Island 2.1 (Level -2)
Learn more about our work on RISC-V: meet Codethink in Paris
If you’re attending RISC-V Summit and would like to learn more about Codethink’s work on RISC-V, let’s set up a meeting. See you in Paris!
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